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System ACE CompactFlash Solution
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DS080 (v1.4) January 3, 2002
Advance Product Specification
Features
* System-Level Features: - High-capacity pre-engineered configuration solution for FPGAs - Chipset configuration solution: * ACETM Controller - Configuration manager * ACE Flash - High-capacity CompactFlashTM storage device - Non-volatile system solution - Flexible configuration interfaces - System configuration rates of up to 30 Mb/s - Board space requirement as low as 25 cm2 ACE Flash (Xilinx-supplied Flash Cards): - Densities of 128 Mbits and 256 Mbits - CompactFlash Type I form factor - PC Card ATA protocol compatible - Noiseless and low CMOS power - Automatic error correction and write retry capabilities - Multiple partitions - Program/erase over full commercial/industrial temperature range Removable storage device Excellent quality and reliability * MTBF >1,000,000 hours * Minimum 10,000 insertions ACE Controller: - CompactFlash interface supports ACE Flash cards, standard third-party CompactFlash (Type I or Type II) cards, and IBM Microdrives with up to 8 Gbit capacity - Configuration of a target FPGA chain through IEEE 1149.1 JTAG with a throughput up to 16.7 Mbits/sec - Interfaces include CompactFlash, JTAG, and MPU - MPU interface is compatible with microprocessor/ microcontroller bus interfaces, such as the IBM PPC405, and Siemens 80C166 - IEEE 1149.1 Boundary-Scan Standard Compliant (JTAG) - FAT12/16 file system - Compact 144-pin TQFP package - Low power -
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General Description
Xilinx developed the System Advanced Configuration Environment (System ACE) family to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with multiple FPGAs. System ACE technology is a ground-breaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high-capacity FPGA systems.
ACE Flash CompactFlash Storage Device
The System ACE family combines Xilinx expertise in configuration control with industry expertise in commodity memories. The first member of the System ACE family uses CompactFlash. As shown in Figure 1, the System ACE CompactFlash solution is a chipset, consisting of a controller device (ACE Controller) and a CompactFlash storage device (ACE Flash).
System ACE Controller Device
128 Mbits or 256 Mbits
Interface to FPGA Target Chain from CompactFlash, MPU, or Test JTAG Port
DS080_01_032101
Figure 1: System ACE Chipset
(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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System ACE CompactFlash Solution Figure 2 shows that the ACE Controller contains multiple interfaces, including CompactFlash, MPU, and JTAG, to allow for a highly flexible configuration solution. For added flexibility, a CompactFlash or IBM Microdrive storage device such as the Xilinx ACE Flash card can be used to store mulPC-Based Tools
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tiple bitstreams, with a capacity of up to 256 Mbits. The combination of the ACE Controller and a standard CompactFlash or IBM Microdrive storage device delivers a powerful configuration solution for high-density FPGA systems.
Boundary-Scan Test Tools
Automatic Test Equipment FPGA Target Chain
Test JTAG Interface (TSTJTAG)
CompactFlash Interface
Configuration JTAG Interface (CFGJTAG)
ACE Flash, Third Party CompactFlash, or IBM Microdrive
MPU Interface
Embedded MPU
DS080_02_032201
Figure 2: ACE Controller Interfaces
ACE Flash Memory Card
The Xilinx ACE Flash memory card is a CompactFlash solid-state storage device that complies with the Personal Computer Memory Card International Association ATA (PCMCIA ATA) specification. The ACE Flash card is available in two densities: 128 Mbits and 256 Mbits. This card contains an on-card intelligent controller that manages interface protocols, data storage and retrieval, ECC, defect handling and diagnostics, power management, and clock control. Using commercially available, low-cost peripheral devices, the ACE Flash card can be programmed independently in a PC environment, in which the Flash card appears as an additional hard drive. Besides these standard options, the System ACE solution allows for in-system programming of an ACE Flash card through the ACE Controller MPU interface. The ACE Flash card also interfaces directly with the ACE Controller to provide a powerful pre-engineered configuration solution. See Figure 3.
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System ACE CompactFlash Solution
Data In/Out
Host Interface
CompactFlash Internal Single Chip Controller
Control
CompactFlash Modules
DS080_03_032101
Figure 3: ACE Flash Card Block Diagram
System ACE File Structure
The System ACE file structure setup allows ACE Flash memory not used for configuration storage to be used as scratchpad memory for other system storage needs. The ability to store multiple bitstreams empowers designers to use a single ACE Flash card to run BIST patterns, PCI applications, or store multiple bitstream variations of a Table 1: ACE Flash Card Capacity Specifications Sectors/Card Capacity (Bits)
128,450,560 256,901,120
design (for example, versions for different geographical regions). The file structure also gives designers the flexibility to store supporting information with the bitstreams in addition to configuration data, such as release notes, user guides, FAQs, or other supporting files.
(Max LBA+1)
31,360 62,720
Number of Heads
2 4
Number of Sectors/Tracks
32 32
Number of Cylinders
490 490
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System ACE CompactFlash Solution
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ACE Controller
The ACE Controller manages FPGA configuration data. The controller provides an intelligent interface between an FPGA target chain and various supported configuration sources; it can target multiple FPGA devices using JTAG at a selectable throughput of up to 16.7 Mbits/sec. As shown in Figure 4, three interfaces are available for configuring a target FPGA chain through the Configuration JTAG Port. These interfaces are: CompactFlash, Microprocessor (MPU), and Test JTAG.
CompactFlash Port
CompactFlash Controller MPU Port
Misc. (LEDs, etc.) Test JTAG (TSTJTAG) Port
DS080_04_030801
MPU Control and Status
CompactFlash Arbiter Test Scan JTAG Interface
Configuration JTAG Controller
Configuration JTAG (CFGJTAG) Port (Target FPGA Chain)
Figure 4: System ACE Controller Block Diagram The directory structure used by the ACE Controller enables it to support both CompactFlash and IBM Microdrive devices through the CompactFlash port. The MPU interface has access to the CompactFlash port, the Configuration JTAG port, and local control/status features. The Test JTAG port is used when doing Boundary-Scan testing of the target FPGA chain or the ACE Controller. Details about each interface are discussed below. The ACE Controller has two main power supplies: the core power supply (VCCL) and a CompactFlash/Test JTAG interface power supply (VCCH). The VCCH power source supplies the Test JTAG and CompactFlash port levels. These two interfaces must be powered at 3.3V. The VCCL core power source supplies the MPU and Configuration JTAG ports, which can be run at 3.3V or 2.5V. It is important to note that these two interfaces are always powered at the same voltage. Considerations for the interface voltage are discussed in Typical Configuration Modes, page 35. See Figure 5.
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System ACE CompactFlash Solution
CompactFlash
I Shaded output
buffers drive VOH = VCCL = 2.5V or 3.3V
I Shaded input
LS LS
LS
LS LS
buffers sense VIH = VCCL = 2.5V or 3.3V
I All non-shaded
TSTJTAG
LS
output buffers drive VOH = VCCH = 3.3V
I All non-shaded
MPU
CORE
input buffers sense VIH = VCCH = 3.3V
I "LS" denotes
level-shifter
I Core voltage level =
VCCL = 2.5V or 3.3V CFGJTAG
DS080_05_030801
Figure 5: ACE Controller I/O Requirements
Status Indicators
The ACE Controller has indicator pins to help monitor device status during operation. Table 2: ACE Controller Status Indicators Name STATLED Pin 95 * * * * * Description When on, the Status LED indicates that configuration is DONE. When blinking, this LED indicates that configuration is still in progress. When off this LED indicates that configuration is in an IDLE state. When on, the ERROR LED indicates that an error occurred. When blinking, this LED indicates that no CompactFlash device was found when the CompactFlash for the Configuration JTAG interface was enabled. * When off, this LED indicates that no errors are detected.
ERRLED
96
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System ACE RESET
CYCLE CLK
Cycle 0
Cycle 1
Cycle 2
Cycle 3
TWRESET THRESET TSRESET
RESET
ds080_56_071801
Figure 6: System ACE RESET Function Timing Diagram
Table 3: System ACE RESET Symbol TW(RESET) TH(RESET) TS(RESET) Parameter System ACE Controller Reset pulse width Reset hold time after rising edge of CLK System ACE Controller Reset setup up time before rising edge of CLK Min 3(1) 0 7(1) Max Units rising edges ns ns
Notes: 1. When using the System ACE Controller RESET, TSRESET + TWRESET of three rising edges of CLK is required.
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System ACE CompactFlash Solution
Interfaces Overview
This section discusses the details of each supported ACE Controller interface. The CompactFlash interface is comprised of two pieces: a CompactFlash Controller, and a CompactFlash Arbiter. The CompactFlash Controller detects the presence and maintains the status of the CompactFlash device. This Controller also handles all CompactFlash device access bus cycles, and abstracts and implements CompactFlash commands such as soft reset, identify drive, and read/write sector(s). The CompactFlash Arbiter controls the interface between the MPU and the Configuration JTAG Controller for access to the CompactFlash data buffer. CompactFlash devices are compliant with multiple read and write modes. The System ACE Configuration Controller supports ATA Common Memory Read and Write functions specifically. Figure 7 and Figure 8 provide detailed timing information on these functions.
CompactFlash Interface (CF)
The CompactFlash interface is the key ACE Controller interface for high-capacity systems. The CompactFlash port can accommodate Xilinx ACE Flash cards, any standard CompactFlash module, or IBM Microdrives up to 8 Gbits, all with the same form factor and board space requirements. The use of standard CompactFlash devices gives system designers access to high-density Flash in a very efficient footprint that does not change with density. CompactFlash is a removable medium, which makes changes and/or upgrades to the memory contents or density simple.
ADDRESS T SU (A) REG T SU (CE) CE T W (WE) WE T W (WT) WAIT T V (WT-WE) DIN T SU (D - WEH) DIN Valid
DS080_09_031301
T REC (WE)
T H (CE)
T V (WT) T H (D)
Figure 7: ACE Flash ATA Memory Write Timing Diagram Table 4: Common Memory Write Timing Item Data Setup before WE Data Hold following WE WE Pulse Width Address Setup Time CE Setup before WE Write Recovery Time CE Hold following WE Wait Delay Falling from WE WE HIGH from Wait Release Wait Width Time (Default Speed) TH(D) TW(WE) TSU(A) TSU(CE) TREC(WE) TH(CE) TV(WT-WE) TV(WT) TW(WT) Symbol TSU(D-WEH) IEEE Symbol tDVWH tlWMDX tWLWH tAVWL tELWL tWMAX tGHEH tWLWTV tWTHWH tWTLWTH 0 350 Min (ns) 80 30 150 30 0 30 20 35 Max (ns)
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AD D R ESS ADDRESS T SU (A) R EG REG T SU (CE) CE CE T A (OE) OE T W (WT) W AI T WAIT T V (WT-OE) (W T-OE) DOUT DOUT
DS080_10_031301
T H (A)
T H (CE)
T V (WT)
T DIS (OE)
Figure 8: ACE Flash ATA Memory Read Timing Diagram Table 5: I/O Read Timing Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD REG Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IORD Data Delay from Wait Rising Wait Width Time (Default Speed) Symbol TD(IORD) TH(IORD) TW(IORD) TSU A(IORD) TH A(IORD) TSU CE(IORD) TH CE(IORD) TSU REG(IORD) TH REG(IORD) TDF INPACK(IORD) TDR INPACK(IORD) TDF IOIS16(ADR) TDR IOIS16(ADR) TD WT(IORD) TD(WT) TW(WT) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH tlGLWTL tWTHQV tWTLWTH 0 165 70 20 5 20 5 0 0 45 45 35 35 35 0 350 Min (ns) Max (ns) 100
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System ACE CompactFlash Solution
A basic understanding of the typical System ACE file and directory structure (shown in Figure 9) is useful when programming an FPGA target system with a CompactFlash device in the System ACE solution.
Available Collections
CompactFlash Rev_1 (sub-dir) Rev_2 (sub-dir) Rev_3 (sub-dir) asia (sub-dir) *.ace europe (sub-dir) *.ace diag_2 (sub-dir) *.ace
Project Name - (root dir) "/" xilinx.sys dir = Rev_3; cfgaddr0 = asia; cfgaddr1 = europe; cfgaddr3 = samerica; cfgaddr4 = diag_1; cfgaddr5 = diag_1; cfgaddr6 = diag_2; cfgaddr7 = diag_2;
ACE System File Containing Active Collection (Up to 8 Designs)
Collection Rev_3 Available Designs for Target FPGA Chain
DS080_11_032101
Figure 9: System ACE Directory Structure The .ACE file is at the lowest level of the directory structure. The Xilinx System ACE software converts a revision of a design (bitstream) into an .ACE file. An .ACE file represents a single set of bitstreams for a particular chain of devices. The next level up in the file structure is a collection. The collection consists of eight .ACE files grouped together. All of the .ACE files in a collection (directory) can be addressed when in the System ACE environment. There can be several collections stored on a CompactFlash device, but only one collection can be active at any given time. The xilinx.sys file determines the collection from which designs can be read. The hierarchical design of the System ACE directory structure provides the ability to maintain multiple revisions or collections of different designs in a single ACE Flash device. Each collection directory can contain one or more designs that reside in different subdirectories. Each design subdirectory should contain a single .ACE file that represents a single set of bitstreams for a particular chain of devices. In addition to FPGA configuration information, the collection and design subdirectories can contain other information pertaining to the system design such as system software, documentation, etc. The xilinx.sys file in the root directory of the ACE Flash device is used to control which of the designs within the active collection is to be used to configure the chain of target devices. Only one collection, containing up to eight designs, can be active at one time. The ACE Controller parses the xilinx.sys file to determine the active collection designs and uses the three configuration address pins or MPU register bits (CFGADDR) to select the desired design. If no xilinx.sys file exists in the root directory of the ACE Flash device, a single .ACE file in the root directory is used by System ACE as the active design. Following are rules for the System ACE directory structure: * * * System ACE configuration files must reside on the first partition of the CompactFlash device. The System ACE partition must be formatted as FAT12 or FAT16. A xilinx.sys or single .ACE file must be in the root (project) directory. An .ACE file is used only if the xilinx.sys file cannot be found in this directory. Only one .ACE file should exist in the ROOT and/or design directories. This directory structure allows the Configuration controller to be able to use the .ACE file to program the FPGA target system correctly.
*
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Microprocessor Interface (MPU)
The MPU Interface provides a useful means of monitoring the status of and controlling the System ACE Controller, as well as ACE Flash card READ / WRITE data. The MPU is not required for normal operation, but when used, it provides numerous capabilities. This interface enables communication between an MPU device and a CompactFlash module and the FPGA target system. The MPU interface is composed of a set of registers that provide a means for communicating with CompactFlash control logic, configuration control logic, and other resources in the ACE Controller. Specifically, this interface can be used to read the identity of a CompactFlash device and read/write sectors from or to a CompactFlash device. The MPU interface can also be used to control configuration flow. The MPU interface enables monitoring of ACE Controller configuration status and error conditions. The MPU interface can be used to delay configuration, start configuration, determine the source of configuration (CompactFlash or MPU), control the bitstream version, reset the device, etc. Two important issues should be understood when using the microprocessor port: Table 6: MPU Interface Port Signal Description Name MPA MPD Width 7 16 Direction In In/Out Active N/A N/A Description Synchronous address inputs. The internal address register is loaded by MPA by a combination of the rising edge of CLK and MPCE LOW. Synchronous data input/output pins. Both the data input and output path are registered and triggered by the rising edge of CLK. Synchronous active LOW chip enable. MPCE LOW is used to enable the MPU interface. MPCE LOW is also used in conjunction with MPOE LOW to enable the MPD output. Synchronous active LOW write enable. A high-to-low-to-high transition must occur on MPWE in three consecutive clock cycles in order for the write to take place.During a valid write cycle, MPCE must be LOW and MPD must be valid during the clock cycle that MPWE. Asynchronous active LOW output enable. Both MPOE and MPCE must be LOW to read from the MPU interface. When either MPOE or MPCE is HIGH, the MPD pins of the ACE Controller are in a high-impedance state. Synchronous active HIGH buffer ready output. During data buffer read mode MPBRDY is HIGH when the data in the DATABUF buffer is valid. During data buffer write mode MPBRDY is HIGH when data can be written to the DATABUF buffer. Synchronous active HIGH interrupt request output. MPIRQ HIGH indicates that an interrupt condition has occurred in the MPU interface. All interrupt conditions must be manually cleared before MPIRQ will go LOW. MPIRQ is always LOW when interrupts are disabled. * * For the controller to be properly synchronized, the MPU must provide the clock. The MPU must comply with System ACE timing diagrams.
This general-purpose microprocessor interface can update the CompactFlash, read the ACE status or obtain direct access to the JTAG configuration ports using the ACE Microprocessor commands. This interface supports either 8-bit (default) or 16-bit data transfers. The bus width can be configured dynamically. All communications between the ACE Controller and a host microprocessor involve transfer of data to or from ACE registers. There are 128 addressable registers in 8-bit mode and 64 addressable registers in 16-bit mode. For easy selection of a new configuration from CompactFlash data, the MPU interface allows for easy reconfiguration of an FPGA chain or capability. The following sections describe supported operations when using the MPU interface.
MPU Port Signal Description
MPU interface port signals are described in Table 6.
MPCE
1
In
LOW
MPWE
1
In
LOW
MPOE
1
In
LOW
MPBRDY
1
Out
HIGH
MPIRQ
1
Out
HIGH
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System ACE CompactFlash Solution
MPU Timing Description
This section contains timing diagrams for the MPU interface. Parameters used in the timing diagrams are described in Table 7. Table 7: MPU Interface Timing Parameters Symbol tSA tSCE tSWE tSOE tSD tDD tDOE tDBRDY tH Address setup time Chip enable setup time Write enable setup time Output enable setup time Data setup time Clock HIGH to valid data Chip/Output enable LOW to valid data Clock HIGH to buffer ready valid Hold time Parameter Min 4 4 12 12 4 ---0 Max -----22 13 22 -Units ns ns ns ns ns ns ns ns ns
Single Register Read Cycle The single register read cycle is shown in Figure 10. A single register read is accomplished by asserting a valid address (MPA), asserting the chip enable (MPCE = LOW) and de-asserting the write enable (MPWE = HIGH) during the first clock cycle (Cycle 0). These signals should hold these values at least until the rising edge of the fourth clock cycle (Cycle 3).
40ns CYCLE CLK
tSA Cycle 0
The output enable signal should be asserted (MPOE = LOW) during the third clock cycle (Cycle 2). Register data associated with the specified address appears on the MPD bus two clock cycles after the falling edge of MPCE during the assertion of MPCE. The register read cycle is then completed by de-asserting the output enable during the fourth clock cycle (Cycle 3).
60ns
Cycle 1
80ns
100ns
Cycle 2
120ns
Cycle 3
140ns
160
Cycle 4
tH ADDRESS tDD tDD DATA tDOE tDOE tH
MPA
MPD
tSCE
MPCE
tSWE tH
MPWE
tDOE tDOE tH tSOE tSOE tH
MPOE
DS080_14_013101
Figure 10: Single Read From an ACE Register
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System ACE CompactFlash Solution Single Register Write Cycle The single register write cycle is shown in Figure 11. A single register write is accomplished by asserting a valid address (MPA), asserting the chip enable (MPCE = LOW) and de-asserting the output enable (MPOE = HIGH) during the first clock cycle (Cycle 0). These signals should hold these values at least until the rising edge of the third clock cycle (Cycle 2).
60ns CYCLE CLK
tSA tH Cycle 0
R
The write enable signal should be asserted (MPWE = LOW) during the second clock cycle (Cycle 1). Data (MPD) to be written to the specified address should be asserted during the same clock cycle that the write enable is asserted (Cycle 1). The register write cycle is then completed by de-asserting the write enable during the third clock cycle (Cycle 2).
80ns
100ns
Cycle 1
120ns
Cycle 2
140ns
160 s
Cycle 3
MPA
ADDRESS tH tSD
MPD
tSCE
DATA tH
MPCE
tH tSWE tSWE tH
MPWE
tH tSOE
MPOE
DS080_15_013101
Figure 11: Single WORD Write to an ACE Register
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Multiple Register Read Timing The minimum timing requirements for sequential register read cycles are shown in Figure 12. Sequential read cycles are identical to single read cycles, except that the chip enable (MPCE) and write enable (MPWE) signals do not need to be de-asserted between read cycles.
50ns CYCLE CLK
tH tSA tSA ADDRESS <0> tDD tDD ADDRESS <1> tDD DATA <1> tH tDOE tSCE tDOE tDD tH Cycle 0 Cycle 1
100ns
Cycle 2 Cycle 3
150ns
Cycle 4
200ns
Cycle 5 Cycle 6
250 0
Cycle 7
MPA
MPD
DATA <0>
MPCE
tSWE tH
MPWE
tDOE tDOE tH tSOE tSOE tH tSOE tDOE tDOE tH tSOE tH
MPOE
DS080_16_013101
Figure 12: Multiple WORD Reads From ACE Register(s)
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System ACE CompactFlash Solution Multiple Register Write Timing The minimum timing requirements for sequential write cycles are shown in Figure 13. Sequential write cycles are
60ns CYCLE CLK
tH tSA tSA ADDRESS <1> tH tSD tSD DATA <1> tH tH tH Cycle 0
R
identical to single write cycles except that the chip enable (MPCE) and output enable (MPOE) signals do not need to be de-asserted between write cycles.
140ns 160ns
Cycle 3
80ns
100ns
Cycle 1
120ns
Cycle 2
180ns
Cycle 4
200ns
22
Cycle 5
MPA
ADDRESS <0>
MPD
tSCE
DATA <0>
MPCE
tH tSWE tSWE tH tSWE tH tSWE tH
MPWE
tSOE tH
MPOE
DS080_17_020101
Figure 13: Multiple WORD Writes to ACE Register(s) Data Buffer Ready Timing The data buffer ready (MPBRDY) signal indicates whether the data buffer is ready to accept new data during a write cycle or whether the data buffer contains valid data to be read during a read cycle. The data buffer itself is sixteen words deep, where each word is 16 bits wide. The data buffer mode transfer direction is identified by the state of the DATABUFMODE bit in the STATUSREG register: * * DATABUFMODE = 0 indicates data buffer read mode DATABUFMODE = 1 indicates data buffer write mode
The data buffer mode depends on the type of command that was issued to the ACE Controller. If an IdentifyMemCard or ReadMemCard command was issued, then the data buffer remains in read mode until the command is finished executing (i.e., all sector data has been read from the buffer). If a WriteMemCard command was issued, then the data buffer remains in write mode until the command is finished executing (i.e., all sector data has been written to the buffer).
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System ACE CompactFlash Solution LOW). Any attempt to read data out of an "empty" data buffer (MPOE = LOW while MPBRDY = LOW) results in invalid data. Valid and invalid data buffer reads are shown in Figure 14.
Data Buffer Read Cycle Ready Timing When the data buffer is in read mode and the last data word is read from the buffer, the data buffer ready signal will go inactive (MPBRDY = LOW) two clock cycles following the last clock cycle that the output enable is active (MPOE =
50ns CYCLE CLK
tH tSA Cycle 0 Cycle 1
100ns
Cycle 2 Cycle 3
150ns
Cycle 4
200ns
Cycle 5 Cycle 6
250
Cycle 7
tH
tSA DATABUFREG ADDRESS tDD tDD DATABUFREG ADDRESS tDD INVALID DATA tH tDOE tDOE tDD
MPA
MPD
VALID DATA
tSCE
MPCE
tSWE tH
MPWE
tDOE tDOE tH tSOE tSOE tH tSOE tDOE tDOE tH tSOE tH
MPOE
tDBRDY
MPBRDY
DS080_18_020101
Figure 14: Valid and Invalid Reads From DATABUFREG Data Buffer
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System ACE CompactFlash Solution Data Buffer Read Cycle Ready Timing When the data buffer is in write mode and the last available space for a data word has been filled, the data buffer ready signal will go inactive (MPBRDY = LOW) two clock cycles following the last clock cycle that the write enable is active
60ns CYCLE CLK
tH tSA tSA DATABUFREG ADDRESS tH tSD tSD INVALID DATA tH tH tH Cycle 0
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(MPWE = LOW). Any attempt to write data to a "full" data buffer (MPWE = LOW while MPBRDY = LOW) does not result in a successful write to the buffer. Valid and invalid data buffer writes are shown in Figure 15.
80ns
100ns
Cycle 1
120ns
Cycle 2
140ns
160ns
Cycle 3
180ns
Cycle 4
200ns
220
Cycle 5
MPA
DATABUFREG ADDRESS
MPD
tSCE
VALID DATA
MPCE
tH tSWE tSWE tH tSWE tH tSWE tH
MPWE
tSOE tH
MPOE
tBRDY
MPBRDY
DS080_19_020101
Figure 15: Valid and Invalid Writes to DATABUFREG Data Buffer
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System ACE CompactFlash Solution The MPU interrupt request line (MPIRQ) remains active HIGH until the RESETIRQ bit is set. The MPIRQ line becomes inactive LOW two cycles after the completion of the RESETIRQ write cycle (Cycle 4). For subsequent MPU interrupt requests to be enabled, the RESETIRQ bit must be reset and one of the three IRQ enable bits (DATABUFRDYIRQ, ERRORIRQ, and/or CFGDONEIRQ) in the CONTROLREG register should be set.
Interrupt Timing
The interrupt request and clearing cycles are shown in Figure 16. In Figure 16, the interrupt request (MPIRQ = HIGH) occurs sometime before Cycle 0. The interrupt request is cleared by performing a single MPU write cycle that sets RESETIRQ = 1 (bit number 11) in the CONTROLREG(15:0) register (BYTE address 0x19 or WORD address 0x0C).
0ns CYCLE CLK 50ns
Cycle 0
100ns
Cycle 1 Cycle 2
150ns
Cycle 3 Cycle 4
tSA
tH
MPA
CONTROLREG(15:0) ADDRESS tH tSD
MPD
tSCE
0800h tH
MPCE
tH tSWE tSWE tH
MPWE
tH tSOE
MPOE
tDIRQ tDIRQ
MPIRQ
DS080_44_030501
Figure 16: Interrupt Request Timing
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Register Specification
The BYTE-mode register space of the MPU interface is shown in Table 8. Table 8: Register Address Map (BYTE Mode Addresses) BYTE Address (MPA [6:0]) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E through 0x3F Even Values 0x40 through 0x7E Odd Values 0x41 through 0x7F Register Name BUSMODEREG BUSMODEREG --STATUSREG(7:0) STATUSREG(15:8) STATUSREG(23:16) STATUSREG(31:24) ERRORREG(7:0) ERRORREG(15:8) ERRORREG(23:16) ERRORREG(31:24) CFGLBAREG(7:0) CFGLBAREG(15:8) CFGLBAREG(23:16) CFGLBAREG(27:24) MPULBAREG(7:0) MPULBAREG(15:8) MPULBAREG(23:16) MPULBAREG(27:24) SECCNTCMDREG(7:0) SECCNTCMDREG(15:8) VERSIONREG(7:0) VERSIONREG(15:8) CONTROLREG(7:0) CONTROLREG(15:8) CONTROLREG(23:16) CONTROLREG(31:24) FATSTATREG(7:0) FATSTATREG(15:8) -DATABUFREG(7:0) DATABUFREG(15:8) Width 1 1 --8 8 8 8 8 8 8 8 8 8 8 4 8 8 8 4 8 8 8 8 8 8 8 8 8 8 -8 8 Mode RW RW --R R R R R R R R R R R R RW RW RW RW RW RW R R RW RW RW RW R R -RW RW Contains information about the FAT table of the first valid partition found in the CompactFlash device. Reserved Address range that provides read and write access to the data buffer. Used to control ACE Controller operations Sector count and CompactFlash command register Version register Logical block address used by the MPU interface during CompactFlash data transfers Logical block address used by the Configuration Controller during CompactFlash data transfers Used to indicate any existing error condition Description Used to control the data bus access mode (8-bit BYTE mode or 16-bit WORD mode) Reserved Reserved Used to monitor ACE Controller status
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System ACE CompactFlash Solution
The 16-bit WORD mode register space of the MPU interface is shown in Table 9. Table 9: Register Address Map (WORD Mode Addresses) WORD Address (MPA [6:1]) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F through 0x1F 0x20 through 0x3F
Register Name BUSMODEREG -STATUSREG(15:0) STATUSREG(31:16) ERRORREG(15:0) ERRORREG(31:16) CFGLBAREG(15:0) CFGLBAREG(27:16) MPULBAREG(15:0) MPULBAREG(27:16) SECCNTCMDREG(15:0) VERSIONREG(15:0) CONTROLREG(15:0) CONTROLREG(31:16) FATSTATREG(15:0) -DATABUFREG(15:0)
Width 1 -16 16 16 16 16 12 16 12 16 16 16 16 16 -16
Mode RW -R R R R R R RW RW RW R RW RW R -RW
Description Used to control the data bus access mode (8-bit BYTE mode or 16-bit WORD mode) Reserved Used to monitor ACE Controller status
Used to indicate any existing error condition
Logical block address used by the Configuration Controller during CompactFlash data transfers Logical block address used by the MPU interface during CompactFlash data transfers Sector count and CompactFlash command register Version register Used to control ACE Controller operations
Contains information about the FAT table of the first valid partition found in the CompactFlash device. Reserved Address range that provides read and write access to the data buffer.
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System ACE CompactFlash Solution BUSMODEREG Register (BYTE address 00h-01h, WORD address 00h)
R
The BUSMODEREG register is used to control the mode of the MPU address and data bus. The single-bit BUSMODEREG register is aliased across two BYTE addresses (0x00-0x01) and one 16-bit WORD address (0x0). This register aliasing ensures that the MPU bus mode can be set regardless of the mode of the microprocessor that is communicating with the ACE Controller. Table 10 provides a description of the BUSMODEREG register bits. Table 10: BUSMODEREG Register Bit Descriptions Bit 0 Name BUSMODE0 Description The BUSMODE bits are used to select the width of the data bus portion of the Microprocessor/MultiLINX bus (default is 0): * When 0, the MPU interface is in BYTE mode (all MPU address bits are used, but only MPU data bits 7:0 are used). * When 1, the MPU interface is in WORD mode (all MPU data bits are used, but only MPU address bits 6:1 are used). Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1 2 3 4 5 6 7
--------
STATUSREG Register (BYTE address 04h-07h, WORD address 02h-03h) The STATUSREG register allows a microprocessor to monitor important ACE Controller operating modes. This is also the register that is read upon receiving an IRQ request in order to identify an interrupt source. Table 11 provides a description of the STATUSREG register bits. Table 11: STATUSREG Register Bit Descriptions Bit 0 Name CFGLOCK Description Configuration controller lock status: * 0 means that the configuration controller does not currently have a lock on the CompactFlash controller resource * 1 means that the configuration controller has successfully locked the CompactFlash controller resource MPU interface lock status: * 0 means that the MPU interface does not currently have a lock on the CompactFlash controller resource * 1 means that the MPU interface has successfully locked the CompactFlash controller resource Configuration Controller error status: * 0 means that no Configuration Controller error condition exists * 1 means that an error has occurred in the Configuration Controller (check the ERRORREG register for more information) CompactFlash Controller error status: * 0 means that no CompactFlash Controller error condition exists * 1 means that an error has occurred in the CompactFlash controller (check the ERRORREG register for more information)
1
MPULOCK
2
CFGERROR
3
CFCERROR
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System ACE CompactFlash Solution
Table 11: STATUSREG Register Bit Descriptions (Continued) Bit 4 Name CFDETECT Description CompactFlash detect flag: * 0 means that no CompactFlash device is connected to the ACE Controller * 1 means that a CompactFlash is connected to the ACE Controller Data buffer ready status: * 0 means that the data buffer is not ready for data transfer * 1 means that the data buffer is ready for data to be transferred out of the buffer when reading from the CompactFlash controller or into the buffer when writing to the CompactFlash or Configuration controller Data buffer mode status: * 0 means read-only mode * 1 means write-only mode Configuration DONE status: * 0 means that the configuration process has not completed * 1 means that the entire ACE Controller configuration file has been executed and configuration of all devices in the target Boundary-Scan chain is complete Ready for CompactFlash controller command: * 0 means not ready for command * 1 means ready for command Configuration mode pin (note that this can be overridden by the CFGMODE bit in the CONTROLREG register): * 1 means automatically start the configuration process immediately after ACE Controller Reset * 0 means wait for CFGSTART bit in CONTROLREG before starting the configuration process Reserved Reserved Reserved Configuration address pins that are used as an offset into the system configuration file in the CompactFlash device used to locate the ACE Controller configuration data file (note that these pins can be overridden by the contents of the CFGADDRBIT[2:0] of the CONTROLREG register) Reserved CompactFlash BUSY bit (reflects the state of the BSY bit in the status register of the CompactFlash device): * 0 means that the CompactFlash device is not busy * 1 means that the CompactFlash command register and data buffer cannot be accessed; Bits 1-6 of the STATUSREG register are not valid when this bit is set CompactFlash ready for operation bit (reflects the state of the RDY bit in the status register of the CompactFlash device): * 0 means the CompactFlash device is NOT ready to accept commands * 1 means CompactFlash device is ready to accept commands CompactFlash data write fault bit (reflects the state of the DWF bit in the status register of the CompactFlash device): * 0 means that a write fault has NOT occurred * 1 means that a write fault has occurred
5
DATABUFRDY
6
DATABUFMODE
7
CFGDONE
8
RDYFORCFCMD
9
CFGMODEPIN
10 11 12 13 14 15 16 17
---CFGADDRPIN0 CFGADDRPIN1 CFGADDRPIN2 -CFBSY
18
CFRDY
19
CFDWF
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System ACE CompactFlash Solution Table 11: STATUSREG Register Bit Descriptions (Continued) Bit 20 CFDSC Name Description CompactFlash ready bit (reflects the state of the DSC bit in the status register of the CompactFlash device): * 0 means that the CompactFlash device is NOT ready * 1 means that the CompactFlash device is ready CompactFlash data request bit (reflects the state of the DRQ bit in the status register of the CompactFlash device): * 0 means that no data is ready to be transferred to/from the data buffer of the CompactFlash device * 1 means that information be transferred to/from the data buffer of the CompactFlash device CompactFlash correctable error bit (reflects the state of the CORR bit in the status register of the CompactFlash device): * 0 means that a correctable data error was NOT encountered * 1 means that a correctable data error was encountered (check the ERRORREG register for more information) CompactFlash ERROR bit (reflects the state of the ERR bit in the status register of the CompactFlash device): * 0 means that no error has occurred during the execution of the previous command * 1 means that the previous command has ended in some type of error (check the ERRORREG register for more information) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
21
CFDRQ
22
CFCORR
23
CFERR
24 25 26 27 28 29 30 31
---------
ERRORREG Register (BYTE address 08h-0Bh, WORD address 04h-05h) The ERRORREG register identifies specific information on any error conditions that might exist in the ACE Controller. Table 12 provides a description of the ERRORREG register bits. Table 12: ERRORREG Register Bit Descriptions Bit 0 Name CARDRESETERR Description CompactFlash card reset error: * 0 means no error * 1 means that the CompactFlash card has failed to reset properly before a time-out condition occurred CompactFlash card ready error: * 0 means no error * 1 means that the CompactFlash card has failed to become properly ready for commands before a time-out condition occurred CompactFlash card read error: * 0 means no error * 1 means that a CompactFlash data read command (either ReadMemCardData or IdentifyMemCard) has failed
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1
CARDRDYERR
2
CARDREADERR
22
R
System ACE CompactFlash Solution
Table 12: ERRORREG Register Bit Descriptions (Continued) Bit 3 Name CARDWRITEERR Description CompactFlash card write error: * 0 means no error * 1 means that a CompactFlash data write command (WriteMemCardData) has failed CompactFlash sector ready: * 0 means no error * 1 means that a sector has failed to become properly valid during a CompactFlash read or write command before a time-out condition occurred CFGADDR error: * 0 means no error * 1 means that the CFGADDR (i.e., the CFGADDR(15:0) register or CFGADDR(1:0) pins, depending on the state of the FORCECFGADDR bit in the CONTROLREG register) does not correspond to a valid location in the CompactFlash Configuration failure error: * 0 means no error * 1 means that configuration of one or more devices in the target Boundary-Scan chain has failed Configuration read error: * 0 means no error * 1 means that an error occurred while reading configuration information from CompactFlash Configuration instruction error: * 0 means no error * 1 means that an invalid instruction was encountered during configuration Configuration INIT monitor error: * 0 means no error * 1 means that the CFGINIT pin did not go HIGH within 500 ms of the start of configuration Reserved CompactFlash bad block error (reflects the state of the BBK bit in the error register of the CompactFlash device): * 0 means no error * 1 means that a bad block has been detected CompactFlash uncorrectable error (reflects the state of the UNC bit in the error register of the CompactFlash device): * 0 means no error * 1 means that an uncorrectable error has been encountered CompactFlash ID not found error (reflects the state of the IDNF bit in the error register of the CompactFlash device): * 0 means no error * 1 means that the requested sector ID is in error or cannot be found CompactFlash command abort error (reflects the state of the ABRT bit in the error register of the CompactFlash device): * 0 means no error * 1 means that the command has been aborted because of a CompactFlash status condition (i.e., Not Ready, Write Fault) or when an invalid command has been issued
4
SECTORRDYERR
5
CFGADDRERR
6
CFGFAILED
7
CFGREADERR
8
CFGINSTRERR
9
CFGINITERR
10 11
-CFBBK
12
CFUNC
13
CFIDNF
14
CFABORT
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System ACE CompactFlash Solution Table 12: ERRORREG Register Bit Descriptions (Continued) Bit 15 Name CFAMNF Description CompactFlash general error (reflects the state of the AMNF bit in the error register of the CompactFlash device): * 0 means no error * 1 means that a general error has occurred Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-----------------
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System ACE CompactFlash Solution
CFGLBAREG Register (BYTE address 0Ch-0Fh, WORD address 06h-07h) The CFGLBAREG read-only register contains the logical block address used by the ACE Controller configuration logic during CompactFlash read/write operations. The CFGLBAREG register affects only transfers between the ACE Controller configuration logic and the CompactFlash card. The MPU uses a separate set of registers (MPULBAREG(27:0)) to transfer data to and from the CompactFlash card. Table 13 provides a description of the CFGLBAREG register bits. Table 13: CFGLBAREG Register Bit Descriptions Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name CFGLBA00 CFGLBA01 CFGLBA02 CFGLBA03 CFGLBA04 CFGLBA05 CFGLBA06 CFGLBA07 CFGLBA08 CFGLBA09 CFGLBA10 CFGLBA11 CFGLBA12 CFGLBA13 CFGLBA14 CFGLBA15 CFGLBA16 CFGLBA17 CFGLBA18 CFGLBA19 CFGLBA20 CFGLBA21 CFGLBA22 CFGLBA23 CFGLBA24 CFGLBA25 CFGLBA26 CFGLBA27 ----Reserved Reserved Reserved Reserved Description Logical Block Address used during CompactFlash read or write sector commands: each block address points to a sector location which is made up of 512 bytes (i.e., maximum CompactFlash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes)
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System ACE CompactFlash Solution MPULBAREG Register (BYTE address 10h-13h, WORD address 08h-09h)
R
The MPULBAREG read-write register contains the logical block address that is used by the MPU interface during CompactFlash read/write operations. The MPULBAREG register affects only transfers between the MPU interface and the CompactFlash card. ACE Controller configuration logic maintains a separate set of registers (CFGLBAREG(27:0)) for use when transferring data to and from the CompactFlash card. Table 14 provides a description of MPULBAREG register bits. Table 14: MPULBAREG Register Bit Descriptions Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name MPULBA00 MPULBA01 MPULBA02 MPULBA03 MPULBA04 MPULBA05 MPULBA06 MPULBA07 MPULBA08 MPULBA09 MPULBA10 MPULBA11 MPULBA12 MPULBA13 MPULBA14 MPULBA15 MPULBA16 MPULBA17 MPULBA18 MPULBA19 MPULBA20 MPULBA21 MPULBA22 MPULBA23 MPULBA24 MPULBA25 MPULBA26 MPULBA27 ----Reserved Reserved Reserved Reserved Description Logical Block Address used during CompactFlash read or write sector commands: each block address points to a sector location which is made up of 512 bytes (i.e., maximum CompactFlash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes)
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System ACE CompactFlash Solution
SECCNTCMDREG Register (BYTE address 014h-15h, WORD address 0Ah) The SECCNTCMDREG register provides the means for an MPU interface to set the sector count and execute CompactFlash Controller commands. Table 15 provides a description of the SECCNTCMDREG register bits. The SECCNT bits of the SECCNTCMDREG register specify the number of sectors to transfer during each ReadMemCardData or WriteMemCardData command: * A SECCNT value of 1 to 255 indicates to the CompactFlash device that 1 to 255 sectors should be transferred. A SECCNT value of 0 indicates that 256 sectors should be transferred. * If the MPU has NOT successfully locked access to the CompactFlash Controller, then writes to the CMD bits of the SECCNTCMDREG register do not change the value of the register. If the MPU has successfully locked access to the CompactFlash Controller and a non-zero value is written to the CMD bits of the SECCNTCMDREG register, then the specified command is executed by the CompactFlash Controller. If the MPU has successfully locked access to the CompactFlash Controller and a zero value is written to the CMD bits of the SECCNTCMDREG register, there is no effect on the value of the CMD bits. The only way to clear the CMD bits is to issue the cfAbort command, which aborts the currently executing command and waits until the CompactFlash Controller clears the CMD bits. Description Sector Count used during CompactFlash read or write sector commands: each sector is made up of 512 bytes
*
*
*
The CMD bits of the SECCNTCMDREG register identify a specific command to be executed:
Table 15: SECCNTCMDREG Register Bit Descriptions Bit 0 1 2 3 4 5 6 7 8 9 10 Name SECCNT0 SECCNT1 SECCNT2 SECCNT3 SECCNT4 SECCNT5 SECCNT6 SECCNT7 CMD0 CMD1 CMD2 Command value: 0x0 : Reserved 0x1 : ResetMemCard command 0x2 : IdentifyMemCard command 0x3 : ReadMemCardData command 0x4 : WriteMemCardData command 0x5: Reserved 0x6 : Abort command 0x7 : Reserved 11 12 13 14 15 -----Reserved Reserved Reserved Reserved Reserved
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System ACE CompactFlash Solution VERSIONREG Register (BYTE address 16h-17h, WORD address 0Bh)
R
The VERSIONREG register holds the ACE Controller version number in the form of a 4-bit major version field, a 4-bit minor version field, and an 8-bit revision/build number field. Table 16 provides a description of the VERSIONREG register bits. Table 16: VERSIONREG Register Bit Descriptions Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name VERSION0 VERSION1 VERSION2 VERSION3 VERSION4 VERSION5 VERSION6 VERSION7 VERSION8 VERSION9 VERSION10 VERSION11 VERSION12 VERSION13 VERSION14 VERSION15 Major version number: MSB is bit 15, LSB is bit 12 Minor version number: MSB is bit 11, LSB is bit 8 Description Revision / build number: MSB is bit 7, LSB is bit 0
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System ACE CompactFlash Solution
CONTROLREG Register (BYTE address 18h-1Bh, WORD address 0Ch-0Dh) The CONTROLREG register provides the means for the MPU interface to control ACE Controller functionality. Table 17 provides a description of the CONTROLREG register bits. Table 17: CONTROLREG Register Bit Descriptions Bit 0 Name FORCELOCKREQ Description Forces the CompactFlash arbitration logic to grant a lock to the MPU interface based on the value of the LOCKREQ bit of the CONTROLREG register (default is 0): * 0 means do not force MPU lock request (i.e., arbitrate between Configuration Controller and MPU interface) * 1 means force MPU lock request (i.e., do not perform arbitration: grant lock request based only on MPU requests) CF arbitration lock request signal; Once a lock is granted, the LOCKREQ must be de-asserted before the lock is removed (default is 0): * 0 means do not request CompactFlash access lock * 1 means request CompactFlash access lock Forces the overriding of the CFGADDR(1:0) pins in favor of using the CFGADDRBIT(2:0) bits of the CONTROLREG(15:13) register (default is 0): * 0 means use the CFGADDR(1:0) pins * 1 means use the CONTROLREG(15:13) register bits Forces the overriding of CFGMODEPIN in favor of using the CFGMODE bit of the CONTROLREG register (default is 0): * 0 means use CFGMODEPIN * 1 means use the CFGMODE bit of the CONTROLREG register Configuration mode (default is 0): * 1 means automatically start the configuration process immediately after ACE Controller Reset * 0 means wait for CFGSTART bit in CONTROLREG before starting the configuration process Configuration start bit (default is 0): * 0 means do not start configuration * 1 means start configuration process Configuration select (default is 0): * 0 means configure from CompactFlash * 1 means configure from MPU interface Configuration/CompactFlash controller reset (default is 0): * 0 means do not reset * 1 means reset the Configuration and CompactFlash controllers (this also causes a "soft-reset" of the CompactFlash device) Data buffer ready IRQ enable (default is 0): * 1 means interrupts are enabled for when data buffer is ready for transfer of data into or out of the buffer * 0 means data buffer ready interrupts are disabled Error IRQ enable (default is 0): * 1 means interrupts are enabled for when an error occurs * 0 means error interrupts are disabled
1
LOCKREQ
2
FORCECFGADDR
3
FORCECFGMODE
4
CFGMODE
5
CFGSTART
6
CFGSEL
7
CFGRESET
8
DATABUFRDYIRQ
9
ERRORIRQ
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System ACE CompactFlash Solution Table 17: CONTROLREG Register Bit Descriptions (Continued) Bit 10 Name CFGDONEIRQ Description Configuration DONE IRQ enable (default is 0): * 1 means interrupts are enabled for when configuration is DONE * 0 means configuration DONE interrupts are disabled Resets the interrupt request line when a '1' is written to this register bit. Note that a '0' must be written to this register bit in order to re-arm for subsequent interrupt conditions. Inverted ACE Controller CFGPROG pin control (default is 0): * 0 means set the CFGPROG pin to its inactive HIGH state of 1 * 1 means set the CFGPROG pin to its active LOW state of 0 Configuration address register bits that are used as an offset into the system configuration file in the CompactFlash device used to locate the ACE Controller configuration data file (note that these register bits can be used to override the CFGADDR[2:0] pins of the ACE Controller) Reserved for future use. These bits must be set to zero at all times.
R
11 12
RESETIRQ
CFGPROG
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CFGADDRBIT0 CFGADDRBIT1 CFGADDRBIT2 CFGRSVD0 CFGRSVD1 CFGRSVD2 --------------
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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System ACE CompactFlash Solution
FATSTATREG Register (BYTE address 1Ch-1Dh, WORD address 0Eh) The FATSTATREG register contains information about the first valid partition of the CompactFlash device such as the boot record and FAT types found. Table 18 provides a description of the FATSTATREG register bits. Table 18: FATSTATREG Register Bit Descriptions Bit 0 Name MBRVALID Master boot record (MBR) valid flag: * 0 means no MBR was detected * 1 means a valid MBR was found Partition boot record (PBR) valid flag: * 0 means no PBR was detected * 1 means a valid PBR was found Master boot record (MBR) FAT12 flag: * 0 means FAT12 flag is not set in MBR * 1 means FAT12 flag is set in MBR Partition boot record (PBR) FAT12 flag: * 0 means FAT12 flag is not set in PBR * 1 means FAT12 flag is set in PBR Master boot record (MBR) FAT16 flag: * 0 means FAT16 flag is not set in MBR * 1 means FAT16 flag is set in MBR Partition boot record (PBR) FAT16 flag: * 0 means FAT16 flag is not set in PBR * 1 means FAT16 flag is set in PBR Calculated FAT12 flag (based on cluster count): * 0 means not FAT12 (cluster count > 4085) * 1 means FAT12 (cluster count < 4085) Calculated FAT12 flag (based on cluster count): * 0 means not FAT16 (cluster count > 65525) * 1 means FAT16 (4085 < cluster count < 65535) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
1
PBRVALID
2
MBRFAT12
3
PBRFAT12
4
MBRFAT16
5
PBRFAT16
6
CALCFAT12
7
CALCFAT16
8 9 10 11 12 13 14 15
---------
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System ACE CompactFlash Solution DATABUFREG Register (BYTE address 40h-7Fh, WORD address 20h-3Fh)
R
The DATABUFREG register is the portal register to the data buffer that is used to transfer data between the MPU interface and the CompactFlash and/or Configuration controllers. The description of the DATABUFREG register bits are shown in Table 19. Table 19: DATABUFREG Register Bit Descriptions Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Data register: * Data register bits are read-only when the DATABUFMODE bit in the STATUSREG register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1. * DATABUFREG(15:08) are accessible in BYTE and WORD bus modes. * During BYTE bus write mode, if the data buffer is ready, any writes to the DATABUFREG(15:08) bits cause the DATABUFREG(15:00) contents to be written to the data buffer. * During BYTE bus read mode, if the data buffer is ready, the DATABUFREG(15:00) register will hold the current value until the DATABUFREG(15:08) bits are read. After DATABUFREG(15:08) is read, the DATABUFREG(15:00) register is loaded with any pending new data. supports an optional 32-bit identification register. Refer to the 1149.1 Boundary-Scan standard specification for a complete description of the required instructions and detailed information on JTAG. Table 20: ACE Controller TAP Pins Pins TSTTDI (TDI) TSTTDO (TDO) TSTTMS (TMS) TSTTCK (TCK) Description Test Data In Test Data Out Test Mode Select Test Clock Name Description Data buffer portal register: * Data register bits are read-only when the DATABUFMODE bit in the STATUSREG register is a 0, otherwise they are write-only when the DATABUFMODE bit is a 1. * DATABUFREG(07:00) are accessible in BYTE and WORD bus modes.
Test JTAG Interface (TSTJTAG)
The Test JTAG Interface (TSTJTAG) supports 1149.1 Boundary-Scan operations on the ACE Controller and all chained FPGA devices connected to the Configuration JTAG (CFGJTAG) port. This interface can also be used to program the target FPGA chain on the CFGJTAG port, using Xilinx or third-party JTAG programming tools. The ACE Controller is fully compliant with the IEEE 1149.1 Boundary-Scan standard, commonly referred to as JTAG. As shown in Figure 17, a Test Access Port (TAP), instruction decoder, and the required IEEE 1149.1 Registers are included in the ACE Controller to support the mandatory Boundary-Scan instructions. In addition, the Controller also
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System ACE CompactFlash Solution
Boundary Scan Register Identifcation Register Bypass Register Instruction Register
TSTTDI TSTTMS TSTTCK
TAP Controller Logic
1 0
CFGDATA (from core) CFGSEL (from core) CFGTDI
CFGTDO
TSTTDO CFGTCK CFGTMS
DS080_45_030801
Figure 17: Test JTAG Interface Block Diagram The TSTJTAG logic is connected to the CFGJTAG port as long as the CompactFlash and MPU interfaces are not connected to the CFGJTAG port. Outlined in the following sections are the details of the JTAG interface for the ACE Controller. The available Boundary-Scan registers for the ACE Controller are shown in Table 21. Table 21: ACE Controller Boundary-Scan Registers Register Name Instruction Register Boundary-Scan Register Identification Register Bypass Register Register Length 8 bits 109 bits 32 bits 1 bit Description Holds current instruction OPCODE and captures internal device status. Controls and observes input, output, and output enable. Captures device IDCODE. Device bypass.
Instruction Register
The Instruction Register (IR) for the ACE Controller is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. The Instruction Register is parallel loaded with a fixed instruction capture pattern in preparation for an instruction sequence. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. This pattern is illustrated in Table 22. Table 22: Instruction Register Values Loaded into IR During Instruction Scan Sequence IR[7]
CFGINSTRERR (MPU ERRORREG register bit)
IR[6]
CFGFAILED (MPU ERRORREG register bit)
IR[5]
CFGREADERR (MPU ERRORREG register bit)
IR[4]
CFCERROR (MPU STATUSREG register bit)
IR[3]
CFGERROR (MPU STATUSREG register bit)
IR[2]
CFGDONE
IR[1: 0]
01
The optional IDCODE instruction is supported in addition to the mandatory instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST). The binary values for these instructions are listed in Table 23.
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System ACE CompactFlash Solution
R
Table 23: ACE Controller Boundary-Scan Instructions Boundary-Scan Instruction BYPASS SAMPLE/PRELOAD IDCODE EXTEST Binary Code [7:0] 11111111 00000001 00001001 00000000 Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD Operation Enables shifting out 32-bit IDCODE Enables boundary-scan EXTEST operation Description
Boundary-Scan Register
The Boundary-Scan register, which is the primary test data register, is used to control and observe the state of device pins during EXTEST and SAMPLE/PRELOAD instructions. For more information on the System ACE Boundary-Scan register (such as bit sequence, 3-state control, and so forth), refer to the System ACE Boundary-Scan Description Language (BSDL) file available from the software download area at: www.xilinx.com.
Bit Sequence
The bit sequence of the device is obtainable from the Boundary-Scan Description Language (BSDL) Files. These files are available from the software download area at: www.xilinx.com.
Identification Register
The Identification Register known as the IDCODE is a fixed, vendor-assigned value that is used to electronically identify the type of device and the manufacturer for a specific device being tested. The ACE Controller IDCODE register is 32 bits wide. The contents of this register can be shifted out for examination by selecting the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format, described in Table 24: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 Table 24: ACE Controller Identification Register Version 0000 Family 0000001 Array Size 00000000 Manufacturer 00001001001 Required by 1149.1 1
Bypass Register
The last standard 1149.1 Boundary-Scan data register in the ACE Controller is the single flip-flop BYPASS register. It directly passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the UPDATE-DR state.
TAP Timing Characteristics
IEEE 1149.1 boundary-scan (JTAG) testing is performed via the standard 4-wire Test Access Port (TAP). The Boundary Scan timing waveforms and switching characteristics of the TAP are described in Figure 18 and Table 25, respectively.
0ns 50ns
TTCKTAP TTAPTCK
100ns
150ns
2
TSTTMS
TTCKTAP TTAPTCK
TSTTDI TSTTCK
TTCKTDO
TSTTDO
VALID
DS080_46_030801
Figure 18: Test JTAG Boundary-Scan Port Timing Waveforms
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Table 25: System ACE Controller TAP Characteristics Symbol T(TAPTCK) T(TCKTAP) T(TCKTDO) F(TSTTCK) Parameter TSTTMS and TSTTDI setup time before rising edge of TSTTCK TSTTMS and TSTTDI hold times after TSTTCK TSTTCK falling edges to TSTTDO output valid Maximum TSTTCK clock frequency Min 4 0 16 16.7 Max Units ns ns ns MHz
Configuration JTAG Interface (CFGJTAG)
Configuration JTAG Port is the interface between the ACE Controller and the target FPGA chain. This port is accessed when configuring the target FPGA chain of devices via any of the ACE Controller interfaces (Test JTAG, MPU, or CompactFlash). To program or test the FPGA target chain, the data from these interfaces is converted to 1149.1 Boundary-Scan (JTAG) serial data.
Typical Configuration Modes
The four ACE Controller interfaces are designed to work together in a number of different combinations. This section discusses typical user configuration modes. A handful of signals determine which interface provides the configuration data source. Table 26 describes these important signals, and Table 27 shows how they work together to determine which interface will be used. This is especially important when using multiple interfaces in a design, or when not using the default values of these signals. The default values of these signals set the CompactFlash interface as the source of configuration data. Table 26: Configuration Signals Used for Selecting Configuration Modes and Active Design Configuration Signal CFGMODE CFGADDR[2:0] CFGSEL CFGSTART CFGRESET FORCECFGADDR FORCECFGMODE Pin or MPU register bit Pins or MPU register bits MPU register bit MPU register bit MPU register bit (CFGRESET is a subset of the RESET pin) MPU register bit (Overrides value on CFGADDR [2:0] pins) MPU register bit (Overrides value on CFGMODEPIN) Description Default CFGMODEPIN = 1 CFGMODE Register Bit = 0 0 0 0 0 0 0
Table 27: Active Configuration Modes
Configuration Interface CFGMODE (1) CFGSEL CFGSTART CFGRESET
CompactFlash (Configure from CF immediately after reset) CompactFlash (Configure from CF after receiving MPU start signal) Microprocessor (Configure from MPU after receiving MPU start signal) Microprocessor (Configure from MPU) Test JTAG (Configure using the TSTJTAG port)
1 0 1 1 1
0 0 1 1 X
X (2) 1 1 X 0
0 0 0 0 0
Notes: 2. The FORCECFGMODE bit in the CONTROLREG register of the MPU interface can be used to force the CFGMODE register bit to override the ACE Controller CFGMODEPIN. 3. An X entry indicates "don't care".
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System ACE CompactFlash Solution
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CompactFlash (CF) to Configuration JTAG (CFGJTAG) Setup
This setup provides a standard CompactFlash interface for high-density FPGA systems. The CompactFlash interface is the source of configuration data. The data configures the Xilinx FPGA chain through Boundary-Scan (JTAG) using the Configuration JTAG port, as shown in Figure 19.
CompactFlash
BSCAN
ACE Controller Core
MPU TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
*CFCGTCK and CFGTMS lines are driven by ACE Controller Core Logic and are broadcast to all target devices.
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_22_030801
Figure 19: Data Flow Diagram of CF to CFGJTAG The ACE Controller handles all necessary steps to perform configuration from the CF to the target system. The appropriate signal connections for this setup are shown in Figure 20. This setup can be used in conjunction with any of the other interfaces.
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VCC VCC VCC VCC 5.1 k 5.1 k 1.0 k 1.0 k VCC 5.1 k
180
180
RESET
CFRESET
IOWR
CSEL
ERRLED
STATLED
IORD
D(15:0) A(10:0) CE1 CE2 WE
CFRSVD
CFD(15:0) CFA(10:0) CFCE1 CFCE2 CFWE CFOE CFWAIT CFREG CFCD1 CFCD2
RESET
CFGTMS CFGTCK CFGTDI CFGTDO
TMS TCK TDO TDI
CompactFlash Device
OE WAIT REG CD1 CD2
ACE Controller
CFGPROG CFGINIT
Xilinx FPGA Target Chain
PROGRAM INIT
DS080_24_121201
Figure 20: Wiring Diagram for CF to CFGJTAG
CompactFlash (CF) to Microprocessor (MPU) Setup
This setup provides a standard CompactFlash to MPU interface for high-density FPGA systems. This interface provides a great deal of flexibility. The ability to communicate with the CF through the MPU port allows the user to perform many operations, such as being able to switch the programming .ACE file so that it can be used for the target system.
CompactFlash
BSCAN
ACE Controller Core
MPU TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_28_030801
Figure 21: Data Flow Diagram of CF to MPU
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System ACE CompactFlash Solution
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The ACE Controller handles all necessary steps to perform a CF to MPU operation. This setup uses the CF to MPU signals shown in the wiring diagram in Figure 22.
VCC VCC VCC 5.1 k 5.1 k 1.0 k 1.0 k VCC 5.1 k 180
VCC
CFRESET
D(15:0) A(10:0) CE1 REG CE2
CFD(15:0) CFA(10:0) CFCE1 CFREG CFCE2 CFWE CFWAIT CFOE CFCD1 CFCD2
CompactFlash Device
WE WAIT OE CD1 CD2
ACE Controller
MPD(15:0)
STATLED MPBRDY
MPA(6:0)
CFRSVD
RESET
ERRLED
IOWR
IORD
CSEL
180
Refer to the microprocessor or microcontroller data sheet for appropriate signal names.
MPU Device
DS080_27_121201
Figure 22: Wiring Diagram CF to MPU
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MPIRQ
MPWE
MPCE
MPOE
CLK
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System ACE CompactFlash Solution a CompactFlash resource lock is shown in Figure 24. Once the MPU interface has been granted a CompactFlash lock, the MPU interface needs to make sure that the CompactFlash device is ready to receive a command. The process for polling the command readiness indicator is shown in Figure 25.
Reading Sector Data from Compact Flash Control Flow Process
Sector data can be read from the CompactFlash device via the MPU interface of the SystemACE controller by following the control flow sequence shown in Figure 23. The first step in the sequence of accessing the CompactFlash interface is to arbitrate for a lock. The control flow process for obtaining
Read Data from CF
Get CF Lock
Check If Ready For Command * Write LBA bits 7:0 to byte address 10h Write LBA bits 15:8 to byte address 11h Write LBA bits 23:16 to byte address 12h Write LBA bits 27:24 to byte address 13h Write SECCNT bits 7:0 to byte address 14h
Set MPU LBA
Set Sector Count Control
Set ReadMemCardData Command Control
Write CMD bits to byte address 15h
Reset configuration controller
W rite CFGRESET bit = 1 to byte address 18h *Set Buffer Count variable equal to the number of buffers in a sector transfer = ((Sector Count)*(512 Bytes per sector))/ (32 bytes per buffer) = (Sector Count) * (16 buffers per sector) No
Initialize Buffer Count variable*
Read Data Buffer
Decrement Buffer Count variable
Buffer Count equal to 0? Yes Clear configuration controller reset W rite CFGRESET bit = 0 to byte address 18h W rite LOCKREQ bit = 0 to byte address 18h
DS080_48_051701
Data is read. Return success.
Release CF Lock
Figure 23: Reading Sector Data from CompactFlash Control Flow Process
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System ACE CompactFlash Solution Once the CompactFlash device is ready to receive a new command, the following information needs to be written to the MPU interface: 1. The sector address or logical block address (LBA) of the first sector to be transferred should be written to the following MPU address locations: - LBA[7:0] @ MPU byte address 10h - LBA[15:8] @ MPU byte address 11h - LBA[23:16] @ MPU byte address 12h - LBA[27:24] @ MPU byte address 13h (note that only four bits are used in the most significant LBA byte) 2. The number of sectors to be read should be written to the low byte of the SECCNTCMDREG register (MPU byte address 14h) 3. The ReadMemCardData command (03h) should be written to the high byte of the SECCNTCMDREG register (MPU byte address 15h) 4. Reset the CFGJTAG controller by setting the CFGRESET bit (bit 7) of the CONTROLREG register (MPU address 18h) to a 1.
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Immediately after writing the command to the MPU interface, the CFGJTAG controller should be reset before reading the sector data from the data buffer. The control flow process for reading the sector data from the data buffer is shown in Figure 26. After all of the requested sector data has been read, the CFGJTAG controller should be taken out of reset and the CompactFlash lock should be released by setting the LOCKREQ bit (bit 1) and CFGRESET bit (bit 7) of the low byte of the CONTROLREG register (MPU byte address 18h) to a 0. Note that all requested sector data should be read from the data buffer in order to avoid a deadlock situation with the CompactFlash device.
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System ACE CompactFlash Solution controller has locked the CompactFlash resource. In this case, the MPU interface must either wait for the CFGJTAG interface to release the lock or it can force the lock to be released. This is done by resetting the CFGJTAG controller by setting the CFGRESET bit (bit 7) and the FORCELOCKREQ bit (bit 0) in the CONTROLREG register (MPU byte address 18h). The lock request process can be started again after forcing the CFGJTAG controller to release the lock.
Get CompactFlash Lock Control Flow Process
The CompactFlash resource must be arbitrated for before it can be accessed via the MPU interface. The CompactFlash arbitration process is shown in Figure 24. A CompactFlash lock is requested by setting the LOCKREQ bit (bit 1) to a 1 in the CONTROLREG register (MPU address 18h) and polling the MPULOCK bit (bit 1) in the STATUSREG register (MPU byte address 04h). Note that if the CFGLOCK bit (bit 0) in the STATUSREG register (MPU byte address 04h) is set, then the CFGJTAG
Get CF Lock
Initialize timer variable
Set Lock Control
Write LOCKREQ bit = 1 to byte address 18h
Get Lock Status
Read MPULOCK bit from byte address 04h
Decrement timer variable
Yes CF Locked?
CF is locked. Return success.
No No Timer Expired?
Yes
CF is busy. Return timeout error.
DS080_49_051701
Figure 24: Get CompactFlash Lock Control Flow Process
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System ACE CompactFlash Solution
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Check if Ready for a Command Control Flow Process
Before reading or writing sector data, it is important to make sure that the CompactFlash device is ready for a command.
This is done by polling the RDYFORCFCMD bit (bit 0) in the second byte of the STATUSREG register (MPU byte address 05h) until it is set to a 1. This control flow process is shown in Figure 25.
Check If Ready For Command
Initialize timer variable
Get Command Ready Status
Read RDYFORCMD bit from byte address 05h
Decrement timer variable
Ready For Command? No No Timer Expired?
Yes
Ready. Return success.
Yes
Busy. Return timeout error.
DS080_50_051701
Figure 25: Check if Ready for a Command Control Flow Process
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System ACE CompactFlash Solution shown in Figure 27. Once the buffer is ready, then all 32 bytes can be read from the buffer from alternating even and odd byte addresses. Reading from an odd byte address while in BYTE mode causes the FIFO to increment the data word to the next available word in the FIFO. Reading from any data buffer address while in WORD mode will cause the FIFO to increment.
Read Data Buffer Control Flow Process
The control flow process for reading from the data buffer is shown in Figure 26. The SystemACE data buffer is implemented as a 32-byte (16-word) deep FIFO that is aliased across a range of MPU byte addresses (40h through 7Fh) in order to facilitate burst transfers across the MPU interface. Sector data is read from the data buffer by first waiting for the buffer to become ready (i.e., full of sector data), as
Read Data Buffer
Wait for Buffer Ready
Initialize Data Count variable*
*Set Data Count variable equal to the number of data items in a buffer (e.g., 16 bytes or 32 words)
Read data word from buffer
Read data bits 7:0 from byte address 40h Read data bits 15:8 from byte address 41h (Note that the following conditions must be valid for a data read to occur from the CompactFlash data buffer: 1. The data buffer must be ready 2. A single read from byte address 41h must occur that will cause the entire 16bit data register to be overwritten by the buffer with new data)
Decrement Data Count variable
No
Data Count equal to 0? Yes
Buffer is written. Return success.
DS080_51_051701
Figure 26: Read Data Buffer Control Flow Process
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Wait for Buffer Ready Control Flow Process
The readiness of the SystemACE data buffer indicates that the buffer is either full during a ReadMemCardData command execution or empty during a WriteMemCardData command execution. The control flow process for waiting for
the buffer to become ready is shown in Figure 27. The buffer ready status can be obtained from either the DATABUFRDY bit (bit 5) of the STATUSREG register (MPU byte address 04h) or from the MPBRDY pin of the SystemACE controller.
Wait for Buffer Ready
Initialize timer variable
Get Buffer Ready Status
Read DATABUFRDY bit from byte address 04h
Decrement timer variable
Yes Buffer Ready?
Buffer is ready. Return success.
No No Timer Expired?
Yes
Buffer not ready. Return timeout error.
DS080_52_051701
Figure 27: Wait for Buffer Ready Control Flow Process
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Microprocessor (MPU) to CompactFlash (CF) Setup
This setup provides a communication path from the MPU to the CF device. The CompactFlash is the source of the configuration data, and this path enables users to read the contents of the CF device.
CompactFlash
BSCAN
ACE Controller Core
MPU TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_25_030801
Figure 28: Data Flow Diagram of MPU to CF The ACE Controller handles all necessary steps to perform an MPU to CF operation. The necessary signals for this setup are shown in Figure 22.
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Writing Sector Data to Compact Flash Control Flow Process
Sector data can be written to the CompactFlash device via the MPU interface of the SystemACE controller by following the control flow sequence shown in Figure 29. The first step in the sequence of accessing the CompactFlash interface is to arbitrate for a lock. The control flow process for obtaining
a CompactFlash resource lock is shown in Figure 24. Once the MPU interface has been granted a CompactFlash lock, the MPU interface needs to make sure that the CompactFlash device is ready to receive a command. The process for polling the command readiness indicator is shown in Figure 25.
Write Data to CF
Get CF Lock
Check If Ready For Command Write LBA bits 7:0 to byte address 10h Write LBA bits 15:8 to byte address 11h Write LBA bits 23:16 to byte address 12h Write LBA bits 27:24 to byte address 13h Write SECCNT bits 7:0 to byte address 14h
Set MPU LBA
Set Sector Count Control
Set WriteMemCardData Command Control
Write CMD bits to byte address 15h
Reset configuration controller
Write CFGRESET bit = 1 to byte address 18h *Set Buffer Count variable equal to the number of buffers in a sector transfer = ((Sector Count)*(512 Bytes per sector))/ (32 bytes per buffer) = (Sector Count) * (16 buffers per sector) No
Initialize Buffer Count variable*
Write Data Buffer
Decrement Buffer Count variable
Buffer Count equal to 0? Yes Clear configuration controller reset Write CFGRESET bit = 0 to byte address 18h Write LOCKREQ bit = 0 to byte address 18h
DS080_053_051701
Data is written. Return success.
Release CF Lock
Figure 29: Write Data to CompactFlash Control Flow Process
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System ACE CompactFlash Solution 4. Reset the CFGJTAG controller by setting the CFGRESET bit (bit 7) of the CONTROLREG register (MPU address 18h) to a 1. Immediately after writing the command to the MPU interface, the CFGJTAG controller should be reset before writing the sector data to the data buffer. The control flow process for writing the sector data from the data buffer is shown in Figure 30. After all of the required sector data has been written, the CFGJTAG controller should be taken out of reset and the CompactFlash lock should be released. This is done by setting the CFGRESET (bit 7) and LOCKREQ (bit 1) bits of the low byte of the CONTROLREG register (MPU byte address 18h) to a 0, respectively. Note that all requested sector data should be written to the data buffer in order to avoid a deadlock situation with the CompactFlash device.
Once the CompactFlash device is ready to receive a new command, the following information needs to be written to the MPU interface: 1. The sector address or logical block address (LBA) of the first sector to be transferred should be written to the following MPU address locations: - LBA[7:0] @ MPU byte address 10h - LBA[15:8] @ MPU byte address 11h - LBA[23:16] @ MPU byte address 12h - LBA[27:24] @ MPU byte address 13h (note that only four bits are used in the most significant LBA byte) 2. The number of sectors that will be written should be loaded into the low byte of the SECCNTCMDREG register (MPU byte address 14h) 3. The WriteMemCardData command (04h) should be written to the high byte of the SECCNTCMDREG register (MPU byte address 15h)
Write Data Buffer
Wait for Buffer Ready
Initialize Data Count variable*
*Set Data Count variable equal to the number of data items in a buffer (e.g., 16 bytes or 32 words)
Write data word to buffer
Write data bits 7:0 to byte address 40h Write data bits 15:8 to byte address 41h (Note that the following conditions must be valid for a data write to occur to the CompactFlash data buffer: 1. The data buffer must be ready 2. A single write to byte address 41h must occur that will cause the entire 16bit data register to be written to the buffer)
Decrement Data Count variable
No
Data Count equal to 0? Yes
Buffer is written. Return success.
DS080_54_051701
Figure 30: Write Data Buffer Control Flow Process
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Write Data Buffer Control Flow Process
The control flow process for writing to the data buffer is shown in Figure 30. The SystemACE data buffer is implemented as a 32-byte (16-word) deep FIFO that is aliased across a range of MPU byte addresses (40h through 7Fh) in order to facilitate burst transfers across the MPU interface. Sector data is written to the data buffer by first waiting for the buffer to become ready (i.e., empty of any sector data),
as shown in Figure 27. Once the buffer is ready, then all 32 bytes can be written to the buffer to alternating even and odd byte addresses. Writing to an odd byte address while in BYTE mode causes the FIFO to increment the data word to the next available word in the FIFO. Writing to any data buffer address while in WORD mode will cause the FIFO to increment.
Microprocessor (MPU) to Configuration JTAG (CFGJTAG) Setup
This setup provides an MPU to CFGJTAG communication path. The data configures the FPGA system through JTAG via the Configuration JTAG Port.
CompactFlash
BSCAN
ACE Controller Core
MPU TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
*CFCGTCK and CFGTMS lines are driven by ACE Controller Core Logic and are broadcast to all target devices.
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_30_030801
Figure 31: Data Flow Diagram of MPU to CFGJTAG The ACE Controller handles all necessary steps to perform configuration using the MPU communication path to the target system. Figure 32 shows the connections required for this setup.
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VCC
VCC VCC 5.1 k STATLED CFRSVD
180 ERRLED
180
CFGTCK CFGTMS CFGTDO
TCK TMS TDI TDO PROGRAM INIT
ACE Controller
CFGTDI CFGPROG
Xilinx FPGA Target Chain
MPD(15:0)
MPBRDY
MPA(6:0)
CFGINIT MPIRQ
RESET
MPWE
MPOE
MPCE
Refer to the microprocessor or microcontroller data sheet for appropriate signal names.
MPU Device
CLK
DS080_33_121201
Figure 32: Wiring Diagram of MPU to CFGJTAG
Write Data to CFGJTAG Interface Control Flow Process
The target devices in the CFGJTAG chain can also be programmed via the MPU interface as shown in Figure 33. The first step is to arbitrate for the data buffer by requesting a CompactFlash lock as shown in Figure 24. Once the lock has been granted, the following steps should be taken to write configuration data to the CFGJTAG controller: 1. Reset the CFGJTAG controller by setting the CFGRESET bit (bit 7) of the CONTROLREG register (MPU address 18h) to a 1.
2. Select the MPU interface as the source of the configuration data by setting the CFGSEL bit (bit 6) of the CONTROLREG register (MPU byte address 18h) to a 1. 3. Direct the CFGJTAG controller to wait for the MPU interface for the start signal by setting the both the FORCECFGMODE (bit 3) and CFGMODE (bit 4) bits of the CONTROLREG register (MPU byte address 18h) to a 1. 4. Set the configuration start signal by setting the CFGSTART bit (bit 5) of the CONTROLREG register (MPU byte address 18h) to a 1.
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System ACE CompactFlash Solution 5. Take the CFGJTAG controller out of reset by setting the CFGRESET bit (bit 7) of the CONTROLREG register (MPU address 18h) to a 0. 6. At this point, the configuration data should be written to the data buffer (as shown in Figure 30) until configuration is done or until an error is encountered. Note that in either case that an entire buffer's worth of
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data should be written to the buffer to ensure that it gets sent to the CFGJTAG controller. After the configuration information has been written successfully, the CFGDONE bit (bit 7) of the STATUSREG register (MPU byte address 04h) should be set to a 1. If this is not the case, then the other bits of the STATUSREG and ERRORREG register should indicate the status of the configuration process.
Write Data to CFGJTAG
Get CF Lock
Reset configuration controller
Set CFGRESET bit to a 1 at byte address 18h
Select MPU as config data source
Set CFGSEL bit to a 1 at byte address 18h
Direct controller to wait for MPU
Set FORCECFGMODE bit to a 1 at byte address 18h Set CFGMODE bit to a 0 at byte address 18h
Start configuration
Set CFGSTART bit to a 1 at byte address 18h
Clear configuration controller reset
Set CFGRESET bit to a 0 at byte address 18h
Initialize Buffer Count variable*
*Set Buffer Count variable equal to the number of buffers in a transfer
Write Data Buffer
Decrement Buffer Count variable Read status & error bits at byte addresses 04h through 0Bh
Check status of configuration
No
Yes Return error. Error?
No
Buffer Count equal to 0?
Yes
Data written. Return status.
DS080_55_051701
Figure 33: Write Data to CFGJTAG Interface Control Flow Process
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Test JTAG (TSTJTAG) to Configuration JTAG (CFGJTAG) Setup
This setup provides a 1149.1 Boundary-Scan communication path to the target FPGA system. Using this setup, the target system can be configured via JTAG from a JTAG compliant tool.
CompactFlash
BSCAN
ACE Controller Core
MPU
TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
*CFCGTCK and CFGTMS lines are driven by ACE Controller Core Logic and are broadcast to all target devices.
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_32_030801
Figure 34: Data Flow Diagram of TSTJTAG to CFGJTAG (Using Bypass Path)
CompactFlash
BSCAN
ACE Controller Core
MPU
TAP CTRL.
TSTTDI TSTTDO
TDO
TDI
(Test JTAG Port)
*TSTTCK, TSTTMS are multiplexed onto the CFGTCK, CFGTMS lines, respectively and are brodcast to all devices.
CFGTDO
TDI
CFGTDI
TDO
TDI
TDO
TDI
TDO
(Configuration JTAG Port)
DS080_34_051701
Figure 35: Data Flow Diagram of TSTJTAG to CFGJTAG (Using Boundary-Scan Path)
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System ACE CompactFlash Solution
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The ACE Controller handles all necessary steps to perform a configuration from the TSTJTAG to the target system via the CFGJTAG interface. When using the TSTJTAG to CFGJTAG setup, the signals in Figure 36 should be connected.
Test JTAG Interface
TCK
TMS
TDI
TDO
VCC VCC
VCC 180 k 180 k
TSTTDO CFGTMS CFGTCK
TSTTMS
TSTTCK
TSTTDI
TMS TCK TDI TDO
ERRLED 5.1 k STATLED RESET RESET CFRSVD
ACE Controller
CFGTDO CFGTDI
Configuration JTAG Interface (Xilinx FPGA Target Chain)
CFGPROG CFGINIT
PROGRAM INIT
DS080_35_121201
Figure 36: Wiring Diagram of TSTJTAG to CFGJTAG
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System ACE CompactFlash Solution
General Timing Specifications
Table 28: Clock Frequency Characteristics Symbol F(CLK) F(TSTTCK) Parameter System ACE clock frequency Test JTAG clock frequency Min Max 33 16.7 Units MHz MHz
MPU Interface Timing Characteristics
Table 29: MPU Interface Timing Characteristics Symbol TS(MPACLK) TS(MPCECLK) TS(MPDCLK) TS(MPOECLK) TS(MPWECLK) TH(CLKMPA) TH(CLKMPCE) TH(CLKMPD) TH(CLKMPOE) TH(CLKMPWE) TD(CLKMPD) TD(CLKMPBRDY) TD(CLKMPIRQ) TD(MPCEMPD) TD(MPOEMPD) Parameter MPA[6:0] setup time before rising edge of CLK MPCE setup time before rising edge of CLK MPD[15:0] setup time before rising edge of CLK MPOE setup time before rising edge of CLK MPWE setup time before rising edge of CLK MPA hold time after rising edge of CLK MPCE hold time after rising edge of CLK MPD[15:0] hold time after rising edge of CLK MPOE hold time after rising edge of CLK MPWE hold time after rising edge of CLK CLK rising edge to MPD CLK rising edge to MPBRDY CLK rising edge to MPIRQ Propagation delay from MPCE to MPD Propagation delay from MPOE to MPD Min 4 4 4 12 12 0 0 0 0 0 22 22 22 13 13 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CompactFlash Interface Timing Characteristics
Table 30: CompactFlash Interface Timing Characteristics Symbol TS(CFCDCLK) TS(CFDCLK) TS(CFWAITCLK) TH(CLKCFCD) TH(CLKCFD) TH(CLKCFWAIT) TD(CLKCFA) TD(CLKCFCE) TD(CLKCFD) TD(CLKCFOE) TD(CLKCFWE) Parameter CFCD1 and CFCD2 setup time before rising edge of CLK CFD[15:0] setup time before rising edge of CLK CFWAIT setup time before rising edge of CLK CFCD1 and CFCD2 hold time after rising edge of CLK CFD[15:0] hold time after rising edge of CLK CFWAIT hold time after rising edge of CLK CLK rising edge to CFA[10:0] CLK rising edge to CFCE1 and CFCE2 CLK rising edge to CFD[15:0] CLK rising edge to CFOE CLK rising edge to CFWE Min 4 4 4 0 0 0 19 16 19 16 16 Max Units ns ns ns ns ns ns ns ns ns ns ns
Configuration JTAG Interface Timing Characteristics
Table 31: Configuration JTAG Interface Timing Characteristics Symbol TS(CFGADDRCLK) TS(CFGINITCLK) TS(CFGMODEPINCLK) TS(CFGTDICLK) TH(CLKCFGADDR) TH(CLKCFGINIT) TH(CLKCFGMODEPIN) TH(CLKCFGTDI) TD(CLKCFGPROG) TD(CLKCFGTDO) TD(CLKCFGTMS) TD(CLKCFGTCK) Parameter CFGADDR[2:0] setup time before rising edge of CLK CFGINIT setup time before rising edge of CLK CFGMODEPIN setup time before rising edge of CLK CFGTDI setup time before falling edge of CLK CFGADDR[2:0] hold time after rising edge of CLK CFGINIT hold time after rising edge of CLK CFGMODEPIN hold time after rising edge of CLK CFGTDI hold time after falling edge of CLK CLK rising edge to CFGPROG CLK falling edge to CFGTDO CLK falling edge to CFGTMS Propagation delay from CLK to CFGTCK Min 6 11 7 4 0 0 0 0 17 16 20 15 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
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Test JTAG Interface Timing Characteristics
Table 32: Test JTAG Interface Timing Characteristics Symbol TS(TSTTDITSTTCK) TS(TSTTMSTSTTCK) TS(INTSTTCK) TH(TSTTCKTSTTDI) TH(TSTTCKTSTTMS) TH(TSTTCKIN) TD(TSTTCKOUT) TD(TSTTCKCFGTCK) TD(CFGTDITSTTDO) TD(TSTTMSCFGTMS) Parameter TSTTDI setup time before rising edge of TSTTCK TSTTMS setup time before rising edge of TSTTCK All other inputs setup time before rising edge of TSTTCK TSTTDI hold time after rising edge of TSTTCK TSTTMS hold time after rising edge of TSTTCK All other inputs hold time after rising edge of TSTTCK TSTTCK falling edge to all other outputs Propagation delay from TSTTCK to CFGTCK Propagation delay from CFGTDI to TSTTDO Propagation delay from TSTTMS to CFGTMS Min 4 4 5 0 0 0 24 14 11 13 Max Units ns ns ns ns ns ns ns ns ns ns
Miscellaneous Timing Characteristics
Table 33: Miscellaneous Timing Characteristics Symbol TS(RESETCLK) TH(CLKRESET) TH(CLKERRLED) TH(CLKSTATLED) Parameter RESET setup time before rising edge of CLK RESET hold time after rising edge of CLK CLK rising edge to ERRLED CLK rising edge to STATLED Min 7 0 17 17 Max Units ns ns ns ns
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Electrical Characteristics
For more detailed ACE Flash specifications, refer to the CompactFlash Memory Card Product Manual from SanDisk, or visit their website at: www.sandisk.com. Table 34: ACE Flash Card Characteristics Type Description DC Input Voltage 1 2 3 1 2 3 X Input Voltage (VCC = 3.3 V) Input Voltage (VCC = 3.3 V) Input Voltage (VCC = 3.3 V) Output Voltage Output Voltage Output Voltage 3-State Leakage Current Ambient Temperature IxZ IL Symbol VCC VIH VIL VIH VIL VTH VTL VOH VOL VOH VOL VOH VOL IOZ TA Input Leakage Current Pull-Up Resistor Pull-Down Resistor Totempole 3-State N-P Channel P-Channel Only N-Channel Only -10 0 -1 VCC - 0.8 GND + 0.4 10 60 1 A VCC - 0.8 GND + 0.4 V VCC - 0.8 GND + 0.4 V 1.8 1.0 V IOH = -4 mA IOL = 4 mA IOH = -8 mA IOL = 8 mA IOH = -8 mA IOL = 8 mA VOL = GND VOH = VCC 1.5 0.6 V Min -0.3 2.4 0.6 V Typ Max 7.0 Units V V Conditions
C
A VIH = VCC/VIL = GND
IxU IxD OTX OZX OPX ONX
RPU1 RPD1
50 50
500 500
k8 k8
VCC = 5.0 V VCC = 5.0 V IOH & IOL IOH & IOL IOH Only IOL Only
Notes: 1. The minimum pull-up resistor leakage current meets the PCMCIA specification of 10 K8 but is intentionally higher in the CompactFlash Memory Card Series product to reduce power use. x refers to the Type 1, 2, or 3. For example, OT3 refers to Totempole output with a type 3 output drive characteristic.
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Table 35: ACE Controller Absolute Maximum Ratings (for VCCL = 2.5 [V] or VCCL = 3.3 [V]) Description Power Supply Voltage Symbol VCCH(1) VCCL(1) Input Voltage VIH VIL Output Voltage VOH VOL Output Current/Pin Storage Temperature
Notes: 1. VCCH is greater than or equal to VCCL.
Limits GND - 0.3 to 7.0 GND - 0.3 to 4.0 GND - 0.3 to VCCH + 0.5 GND - 0.3 to VCCL + 0.5 GND - 0.3 to VCCH + 0.5 GND - 0.3 to VCCL + 0.5 30 -65 to 150
Units V
V
V mA C
IOUT TSTG
Table 36: ACE Controller Recommended Operating Conditions (for VCCL = 2.5 [V]) Description Power Supply Voltage Symbol VCCH VCCL Input Voltage VIH VIL Ambient Temperature TA Min 3.0 2.25 GND GND -40 Typ 3.3 2.5 - - - Max 3.6 2.75 VCCH VCCL 85(1) Units V
V C
Notes: 1. The ambient temperature range is recommended for TJ = -40 to 125 C.
Table 37: ACE Controller Recommended Operating Conditions (for VCCL = 3.3 [V]) Description Power Supply Voltage Symbol VCCH VCCL Input Voltage VIH VIL Ambient Temperature TA Min 3.0 3.0 GND GND -40 Typ 3.3 3.3 - - - Max 3.6 3.6 VCCH VCCL 85(1) Units V
V C
Notes: 1. The ambient temperature range is recommended for TJ = -40 to 125 C.
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Table 38: ACE Controller Characteristics Description Quiescent Current (between VCCH and GND) Quiescent Current (between VCCL and GND) Input Leakage Current Symbol ICCSH Min -Typ -Max 300 Units A Conditions VI = VCCH or VCCL or GND, VCCH = Max, VCCL = Max, IOH = IOL = 0 VI = VCCH or VCCL or GND, VCCH = Max, VCCL = Max, IOH = IOL = 0 VCCH = Max, VCCL = Max, VIHH = VCCH, VIHL = VCCL, VIL = GND Input Characteristics for I/O Supply Rail VCCH = Max Low-Level Input Voltage VIL1H --0.8 V Input Characteristics for I/O Supply Rail VCCH = Min High-Level Input Voltage VIH1L 2.0 --V Input Characteristics for I/O Supply Rail VCCL = Max Low-Level Input Voltage Pull-Up Resistance Pull-Down Resistance Pull-Up Resistance Pull-Down Resistance High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Off-State Leakage Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance VIL1L RPU1H RPD1H RPU1L RPD1L VOH3H VOL3H VOH3L VOL3L IOZ -40 40 20 20 VCCH - 0.4 -VCCL - 0.4 --1 -100 100 50 50 -----0.8 240 240 120 120 -GND + 0.4 -GND + 0.4 1 V k8 k8 k8 k8 V V V V A Input Characteristics for I/O Supply Rail VCCL = Min VI = GND VI = VCCH VI = GND VI = VCCL VCCH = Min, IOH = -12 mA VCCH = Min, IOL = 12 mA VCCL = Min, IOH = -12 mA VCCL = Min, IOL = 12 mA VCCH = Max, VCCL = Max, VOHH = VCCH, VOHL = VCCL, VOL = GND ----
ICCSL
--
--
420
A
ILI
-1
--
1
A
High-Level Input Voltage
VIH1H
2.0
--
--
V
CI CO CIO
----
----
----
pF pF pF
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Package Specifications: (Package Dimensions and Reliability Data)
.063.002 [1.60] .130.004 [3.30]
26 1 .040.003 [1.00]
50 25 .040.003 [1.00] .039.002 [1.00]
2X .472.004
[12.00]
2X 1.015.003 [25.78]
1.433.006
[36.40]
TO
.030.003 [0.8]
4X R.020.004 [0.5]
1.640.005 [41.66] 1.685.004 [42.80]
.025.003 [0.6]
Figure 37: ACE Flash Card Dimensions
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2X .118.003 [3.00]
P
.096.003 [2.4]
DS080_36_020601
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0.196 [5.0]
0.130 [3.3]
2.126 [54.0]
3.370 [85.6]
1.196 [30.4]
.866 [22.0]
1.536 [39.03] .472 [12.0] .078 [2.0] 1.694 [43.03]
0.138 [3.5]
DS080_37_020601
Figure 38: ACE Flash Card Adapter Dimensions Table 39 shows ACE Flash reliability considerations. Table 39: ACE Flash Reliability MTBF (@ 25 degrees C) Preventative Maintenance Data Reliability Endurance >1,000,000 hours None <1 non-recoverable error in 1014 bits read >= 300,000 erase/program cycles per logical sector
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DS080_47_030801
Figure 39: ACE Controller TQ144 Package Drawing
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Pin Descriptions
This section provides ACE Flash and ACE Controller pinout information.
ACE Flash Card I/O Pins
Table 40 lists ACE Flash signal/pin assignments. LOW active signals have an overline. Pin types are Input, Output, or Input/Output. Table 40: ACE Flash Card Pin Assignments and Pin Types PC Card Memory Mode Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Table 40: ACE Flash Card Pin Assignments and Pin Types (Continued) PC Card Memory Mode
Signal Name
GND D03 D04 D05 D06 D07 CE1 A10 OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 WP CD2 CD1 D11 (1)
Pin Type
I/O I/O I/O I/O I/O I I I I I I
In, Out (2) Type
Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U I1Z I3U I1Z I1Z I1Z Power
Pin Number
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Signal Name
D12 (1) D13 (1) D14 (1) D15 (1) CE2 (1) VS1 IORD IOWR WE RDY/BSY VCC CSEL VS2 RESET WAIT INPACK REG BVD2 BVD1 D08 (1) D09 (1) D10 (1) GND
Pin Type
I/O I/O I/O I/O I O I I I O
In, Out (2) Type
I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U OT1 Power
I O I O O I I/O I/O I/O I/O I/O
I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground
I I I I I I I I/O I/O I/O O O O I/O
I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Ground Ground I1Z,OZ3
Notes: 1. These signals are required only for 16-bit access and not required when installed in 8-bit systems. For lowest power dissipation, leave these signals open. 2. For definitions of In, Out Type, refer to Electrical Characteristics, page 56.
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Table 41 defines the DC characteristics for all ACE Flash input and output type structures. Table 41: ACE Flash Signal Descriptions Signal Name A10 - A0 Dir. I Pin 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20 46 45 26, 25 Description These address lines along with the REG signal are used to select the following: The I/O port address registers within the CompactFlash Card, the memory mapped port address registers within the card, a byte in the card's information structure and its configuration control and status registers. This signal is asserted HIGH as the BVD1 signal since a battery is not used with this product. This output line is always driven to a HIGH state in Memory Mode since a battery is not required for this product. These Card Detect pins are connected to ground on the CompactFlash Card. They are used by the host to determine if the card is fully inserted into its socket. These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. CE2 always accesses the odd byte of the word. CE1 accesses the even byte or the Odd byte of the word depending on A0 and CE2. A multiplexing scheme based on A0, CE1, CE2 allows 8 bit hosts to access all data on D0-D7. See the "Attribute Memory Function" tables in the CompactFlash Memory Card Product Manual. This signal is not used for this mode. These lines carry the Data, Commands and Status information between the host and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word.
BVD1 BVD2 CD1, CD2
I/O I/O O
CE1, CE2
I
7, 32
CSEL D15 - D00
I I/O
39 31, 30, 29, 28, 27, 49, 48, 47, 6, 5, 4, 3, 2, 23, 22, 21 1, 50 43 34 35 9
GND INPACK IORD IOWR OE
-O I I I
Ground. This signal is not used in this mode. This signal is not used in this mode. This signal is not used in this mode. This is an Output Enable strobe generated by the host interface. It is used to read data from the CompactFlash Card in Memory Mode and to read the CIS and configuration registers. In Memory Mode this signal is set HIGH when the CompactFlash Card is ready to accept a new data transfer operation and held LOW when the card is busy. The Host memory card socket must provide a pull-up resistor. At power up and at Reset, the RDY/-BSY signal is held LOW (busy) until the CompactFlash Card has completed its power up or reset function. No access of any type should be made to the CompactFlash Card during this time. The RDY/-BSY signal is held HIGH (disabled from being busy) whenever the following condition is true: The CompactFlash Card has been powered up with RESET continuously disconnected or asserted.
RDY/BSY
O
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System ACE CompactFlash Solution Table 41: ACE Flash Signal Descriptions (Continued) Signal Name REG Attribute Memory Select RESET I 41 Dir. I 44 Pin Description This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. HIGH for Common Memory, LOW for Attribute Memory. When the pin is HIGH, this signal resets the CompactFlash Card. The card is Reset only at power up if this pin is left HIGH or open from power-up. The card is also reset when the Soft Reset bit in the Card Configuration Option Register is set. +5 V, +3.3 V power. Voltage Sense Signals. VS1 is grounded so that the CompactFlash Card CIS can be read at 3.3 volts and VS2 is open and reserved by PCMCIA for a secondary voltage. The WAIT signal is driven LOW by the CompactFlash Card to signal the host to delay completion of a memory or I/O cycle that is in progress. This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. Memory Mode -- the CompactFlash Card does not have a write protect switch. This signal is held LOW after the completion of the reset initialization sequence.
R
VCC VS1 VS2 WAIT
-O
13, 38 33 40
O
42
WE
I
36
WP Write Protect
O
24
ACE Controller I/O Pins
Table 42 lists ACE Controller active pins. Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output)
Pin Name CLK RESET Pin # 93 33 I/O Type IN IN OUT3 STATLED 95 (Open-drain) OUT3 ERRLED MPCE MPWE MPOE MPIRQ MPBRDY MPA00 MPA01 96 (Open-drain) 42 76 77 41 39 70 69 IN IN IN OUT2 OUT2 IN IN VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL Ext. Pull-up Int. Pull-up Int. Pull-up Int. Pull-up N/A N/A N/A N/A VCCL Ext. Pull-up ACE Controller error LED; when LOW, this pin indicates that an error has occurred in the ACE Controller. Chip enable (active LOW) Write enable (active LOW) Output enable (active LOW) Interrupt request flag Data buffer ready flag MPU address line 0 MPU address line 1 I/O Supply Rail VCCL VCCL Termination N/A Int. Pull-up Description ACE Controller system clock ACE Controller reset (active LOW; needs to be active for three clock cycles) ACE Controller status LED
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Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) (Continued)
Pin Name MPA02 MPA03 MPA04 MPA05 MPA06 MPD00 MPD01 MPD02 MPD03 MPD04 MPD05 MPD06 MPD07 MPD08 MPD09 MPD10 MPD11 MPD12 MPD13 MPD14 MPD15 CFA00 CFA01 CFA02 CFA03 CFA04 CFA05 CFA06 CFA07 CFA08 CFA09 CFA10 CFD00 CFD01 CFD02 Pin # 68 67 45 44 43 66 65 63 62 61 60 59 58 56 53 52 51 50 49 48 47 4 142 141 139 137 135 134 132 130 125 121 5 6 8 I/O Type IN IN IN IN IN IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 IN/OUT3 IN/OUT3 IN/OUT3 I/O Supply Rail VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH Termination N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description MPU address line 2 MPU address line 3 MPU address line 4 MPU address line 5 MPU address line 6 MPU data line 0 MPU data line 1 MPU data line 2 MPU data line 3 MPU data line 4 MPU data line 5 MPU data line 6 MPU data line 7 MPU data line 8 MPU data line 9 MPU data line 10 MPU data line 11 MPU data line 12 MPU data line 13 MPU data line 14 MPU data line 15
CompactFlash address line 0 CompactFlash address line 1 CompactFlash address line 2 CompactFlash address line 3 CompactFlash address line 4 CompactFlash address line 5 CompactFlash address line 6 CompactFlash address line 7 CompactFlash address line 8 CompactFlash address line 9 CompactFlash address line 10 CompactFlash data line 0 CompactFlash data line 1 CompactFlash data line 2
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System ACE CompactFlash Solution Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) (Continued)
Pin Name CFD03 CFD04 CFD05 CFD06 CFD07 CFD08 CFD09 CFD10 CFD11 CFD12 CFD13 CFD14 CFD15 CFCE1 CFCE2 CFREG CFWE CFOE CFWAIT CFRSVD CFCD1 CFCD2 CFGADDR0 CFGADDR1 CFGADDR2 Pin # 104 106 113 115 117 7 11 12 105 107 114 116 118 119 138 3 131 123 140 133 103 13 86 87 88 I/O Type IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 OUT2 OUT2 OUT2 OUT2 OUT2 IN IN IN IN IN IN IN I/O Supply Rail VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCL VCCL VCCL Termination N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Ext. Pull-up Int. Pull-up Int. Pull-up Int. Pull-down Int. Pull-down Int. Pull-down Description
R
CompactFlash data line 3 CompactFlash data line 4 CompactFlash data line 5 CompactFlash data line 6 CompactFlash data line 7 CompactFlash data line 8 CompactFlash data line 9 CompactFlash data line 10 CompactFlash data line 11 CompactFlash data line 12 CompactFlash data line 13 CompactFlash data line 14 CompactFlash data line 15 CompactFlash chip enable 1 (active LOW); CompactFlash chip enable 2 (active LOW); CompactFlash register select line (active LOW);
this pin is always driven to a 1 but is provided here for future compatibility.
CompactFlash write enable line (active LOW) CompactFlash output enable line (active LOW) CompactFlash memory cycle wait flag (active
LOW) This pin must be pulled up to VCCH using an external pull-up resistor.
CompactFlash card detect line 1 (active LOW) CompactFlash card detect line 2 (active LOW)
Configuration address select pin 0 Configuration address select pin 1 Configuration address select pin 2 Configuration mode pin: * When 0, this pin instructs the ACE Controller to start the configuration process when the CFGSTART bit is set in the CONTROLREG register in the MPU interface. * When 1, this pin instructs the ACE Controller to start the configuration process immediately following reset. Test JTAG port test data input Test JTAG port test clock
CFGMODEPIN
89
IN
VCCL
Int. Pull-up
TSTTDI TSTTCK
102 101
IN IN
VCCH VCCH
Int. Pull-up N/A
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Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) (Continued)
Pin Name TSTTMS TSTTDO CFGTDO CFGTDI CFGTCK CFGTMS CFGPROG Pin # 98 97 82 81 80 85 79 (Open-drain) I/O Type IN OUT3 OUT3 IN OUT2 OUT3 OUT3 VCCL Ext. Pull-up I/O Supply Rail VCCH VCCH VCCL VCCL VCCL VCCL Termination Int. Pull-up Ext. Pull-up(1) Description Test JTAG port test mode select Test JTAG port test data output Configuration JTAG test data output Configuration JTAG test data input Configuration JTAG test clock Configuration JTAG test mode select Configuration JTAG PROGRAM pin (active LOW); this pin is driven LOW when the ACE Controller PROG instruction is executed. Configuration JTAG INIT pin (active LOW); this pin is used to sense when all devices are ready to be programmed (i.e., INIT = 1 indicates target device(s) are ready to receive configuration data and INIT = 0 indicates that the target device(s) are being cleared and are not ready to be configured) Power-on-reset (POR) bypass input; used in conjunction with POR_RESET to bypass the internal POR circuit in favor of using an external board-level POR circuit; the internal POR circuit is bypassed when POR_BYPASS = 1; the POR_BYPASS pin should be held at a static 0 or 1 while the ACE controller is receiving power. Power-on-reset bypass input; can be used in conjunction with POR_BYPASS to bypass the internal POR circuit in favor of using an external board-level POR circuit; all internal circuitry is reset when POR_BYPASS = 1 and POR_RESET = 1; The POR_RESET pulse duration should be at least 1 microsecond long. Power-on-reset test output; this pin should be a true "no connect" on the board. This pin is Low when it is finished resetting.
Ext. Pull-up(1) Int. Pull-up N/A Ext. Pull-up(1)
CFGINIT
78
IN
VCCL
Int. Pull-up
POR_BYPASS
108
IN
VCCH
Int. Pull-down
POR_RESET
72
IN
VCCH
Int. Pull-down
POR_TEST
74
OUT2
VCCH
N/A
Notes: 1. JTAG 1149.1 requires a pull-up resistor on potentially undriven TDO/TMS signals.
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System ACE CompactFlash Solution Table 43 lists ACE Controller voltage and ground pins. Table 43: ACE Controller Voltage and Ground Pins Pin Name VCCH Pin Number 1 17 37 55 73 92 109 128 VCCL 10 15 25 57 84 94 99 126 GND 9 18 26 35 46 54 64 75 83 91 100 110 111 112 120 129 136 144 Ground pins Low-voltage (2.5V or 3.3V) source pins Description High-voltage (3.3V) source pins Pin Name NC Table 44 lists ACE Controller no-connect pins. Table 44: ACE Controller No-Connect Pins Pin Number 2 14 16 19 20 21 22 23 24 27 28 29 30 31 32 34 36 38 40 71 90 122 124 127 143 Description Pins that must not be connected to any board-level signals, including ground and power planes.
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System ACE CompactFlash Solution
Ordering Information
System ACE Valid Ordering Combinations XCCACE -- TQ144I XCCACE128-I XCCACE256-I Description ACE Controller Chip 128-Mbit ACE Flash Card 256-Mbit ACE Flash Card Package TQ144 CF Type I CF Type I Operating Range (TA = -40 to +85 C) (TA = -40 to +85 C) (TA = -40 to +85 C)
Revision History
Version No. 1.0 1.1 1.2 1.3 1.4 Date 05/18/01 06/04/01 07/18/01 12/12/01 01/03/02 Initial Xilinx release. Corrected Table 27, page 35. CFGMODE is 1 after Reset, 0 after MPU start signal. Updated. Updated. Updated Table 2, Figure 20, Figure 22, Figure 32, Figure 36, and Table 42 (last row only). Description
DS080 (v1.4) January 3, 2002 Advance Product Specification
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